1. Technical Field
The present disclosure relates to an emulation system, and more particularly, to an emulation system for distributed processing of emulation data.
2. Discussion of Related Art
Verification is essential for completion of digital circuits. The verification determines whether a design circuit is normal. When the design circuit is abnormal, debugging is performed to correct the abnormal design circuit to be normal. Typically, the verification is performed using a software simulation or a hardware emulator.
A simulation-based verification method is simple and inexpensive to perform, but needs a relatively large amount of time. On the other hand, an emulator-based verification method is complex and expensive to perform, but needs only a relatively small amount of time.
Typically, commercial emulation methods use a field-programmable gate array (FPGA). For verification of a design circuit, the FPGA needs an additional circuit for extracting the state value of an important net or an important flip-flop in the design circuit. In an FPGA-based verification method, all the state values extracted by the additional circuit are stored in an internal memory and the data stored in the memory are read out using a Joint Test Action Group (JTAG), upon completion of emulation.
In an emulation system, many simulation result data are transferred to a computer through only one high-speed computer interface. As the gate size of a device under test (DUT) increases, the amount of data needed for debugging increases. Therefore, in the emulation system, data transfer time increases with an increase in the data amount, which reduces an emulation speed.
Therefore a need exists for an emulation system for distributed processing of emulation data.